System on Chip (SoC) is a concept that strives to integrate more and more functionality into a given device. This integration can take the form of either hardware or solution software. Performance gains are traditionally achieved by increased clock rates and more advanced process nodes. Many SoC designs pair a digital signal processor (DSP) with a reduced instruction set computing (RISC) processor to target specific applications. A more recent approach to increasing performance has been to create multi-core devices.
Complex SoCs require a scalable and convenient method of connecting a variety of peripheral blocks such as processors, accelerators, shared memory and IO devices while addressing the power, performance and cost requirements of the end application. Due to the complexity and high performance requirements of these devices, the chip interconnect tends to be hierarchical and partitioned depending on the latency tolerance and bandwidth requirements of the endpoints. The connectivity among the endpoints tends to be more flexible to allow for future devices that may be derived from a current device. In this scenario, management of clock signals that are provided to the various modules and components of the complex SoC may require dynamic changes in frequency. In many cases, different clock frequencies are required for different modules and components.
Different clock frequency signals are typically generated using a divider to divide down a higher frequency to a specified operating clock frequency. High speed integer clock dividers that guarantee 50% duty cycle for the output clock have been well understood and used widely in system-on-chip implementations. For example, U.S. Pat. No. 5,442,670, “Circuit for Dividing Clock Frequency by N.5, Where N is an Integer,” describes an implementation that only supports N.5 division and is not easily scalable to support integer division. Further, this implementation may not be appropriate for use in high speed designs (>600 MHz).
U.S. Pat. No. 6,469,549, “Apparatus and Method for Odd Integer Signal Division,” describes an implementation for an integer divider guaranteeing 50% duty cycle when the division ratio is odd.
U.S. Pat. No. 6,617,893, “Digital Variable Clock Divider,” describes an implementation that performs integral and non-integral clock division; however, it may not be practical for high speed implementation (>600 MHz). Also the implementation requires a significant amount of area overhead.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.